Hardware Integration Steps
Startup from home test in winter: PISA: HB + AMS + AM + SC + MRG/(old MRG +lvds?ttl) CHICAGO: GRT + HF + TF
Build up increasing complexity at B0:
- I: HF+HB+AMS+AM+TF+SC (+ old MRG)
- II: add GRT (brings in G-link issues)
- III: add 1 new Merger
- IV: add 2 new Mergers
- V: add XTF
- VI: add XTRP
Adding SVX readout “factorize”, can be done at any time after II.
Same for Level 2 i/f, though not always possible to plug it. Anyhow only needed to check communication.