CLOCK DISTRIBUTION FOR THE AMS January 13, 1999 The AMS uses two Roboclocks. Note that skew for each output pair is controlled by only one pair of pins, so it is has to be the same for both. Also note the different ranges of skew adjustment with respect to feedback: 1Q0,1Q1,2Q0,2Q1 (Q00,Q10,Q01,Q11 in Concept) : 0 +-1 +-2 +-3 +-4 3Q0,3Q1,4Q0,4Q1 (Q02,Q12,Q03,Q13 in Concept) : 0 +-2 +-4 +-6 Therefore if some clock lines need to be swapped to optimise pin assignements, care should be taken to stay in the same "skew range". Also notice that FB is taken from the output pin which is closest to the feeback pin, to avoid line crossing and signal reflection. Destination loads are: Xilinx 73144: 12pF Xilinx 7336: 8pf Cypress CY7C4245 10pF? Cypress 384a: 10pF sockets: unknown ! AS32 TTL: 15 pF ? ROBOCLOCK_1 : uses the quartz oscillator as REF. name skew output# destination chips load(pF) Cypress Cadence ------------------------------------------------------------------------------- CLK1 0 1Q0 Q00 USQ_SREG1 USQ_SREG2 16 CLK2 0 1Q1 Q10 USQ_OREG1 USQ_OREG2 16 CLK3 0 2Q0 Q01 INPUT FIFO1 FIFO2 42? CLK4 0 2Q1 Q11 OUTPUT OSPY 24 WCLK2 0 3Q0 Q02 AS32 for HSPYW_ 15 ? WCLK1 0 3Q1 Q12 AS32 for OUTDS_ AS32 for OSPYW_ 10 ? CLK5 0 4Q0 Q03 VME 12 ICLK6 0 4Q1 Q13 ROBOCLOCK_2 5 ? OUTPUT 3Q0 (Q02) (WCLK2) is used as feedback (FB pin). ROBOCLOCK_2 : uses ICLK6 from roboclock_1 as REF. name skew output# destination chips load(pF) Cypress Cadence ------------------------------------------------------------------------------ CLOCK6 -4 1Q0 Q00 P3 connector A2(CLOCKOUT2) 10 ? CLOCK9 -4 1Q1 Q10 P3 connector A1(CLOCKOUT1=SPARECLOCK1) SPARECLOCK2 0 2Q0 Q01 SPARECLOCK3 0 2Q1 Q11 Used as Feedback. Skew can't be changed 10 CLOCK7 0 3Q0 Q02 INPREG GLUE 22 CLOCK8 0 3Q1 Q12 HSPY 12 SPARECLOCK6 4Q0 Q03 SPARECLOCK7 4Q1 Q13 OUTPUT 2Q1 (Q11) (SPARECLOCK3) is used as feedback (FB pin).