TITLE INPREG CHIP INPREG XEPLD ; INPut REGister XEPLD ; This chip receives the data from the SS RAM and register them so that they ; can be properly and timely presetned at the GLUE input. Only valid hit are ; sent in output, i.e. words whose bit are not all 1's. ; In addition the INPREG XEPLD generates the following control signals: ; NEWHIT to useq. One clock cycle before a new hit is presented ; at INPREG output, so that the useq will assert INPUT opcode ; to the glue. ; EEIN to useq, with the same timing, but instead of NEWHIT, to signal ; that End Event has been detected in input, all valid hits ; have been sent, and thus the useq can assert COUNT at the next ; clock cycle ; INVADD to INPUT XEPLD, to flag invalid SS addresses that result int ; the SS data to be all 1's. This signal is asserted for only the ; clock cycle in which an invalid data is received, it will have ; to be properly registered in the EE_REGISTER and VME_RESGITER ; of the INPUT XEPLD. ; This chip works in pipelined data driven mode, data take 3 clock cycles to ; pass through the chip (i.e. there are 3 registers inside INPREG where data ; are stored at consecutive clock rising edges). ; INput is enabled by a IRE singal coming from INPUT_XEPLD. Two versions of the ; same enable singal are needed: a high active one (IRE) for internal use, and ; a low active one (IRECE_) to be used as clock enable for the input pad ; registers. Input data are stored in the input pad registers for maximum ; speed (minimum setup time), then one clock cycle is used to compute the logic ; AND of all bits in the UIM and decide wether to enable the internal ; INTERMEDIATE REGISTER (IRCE signal). Whenver valid new data are written in ; the intermediate register, NEWHIT (or EEIN) are sent to the microsequencer ; with the same timing as valid data out of intermediate register. At the next ; clock rising edge valid data (NEWHIT case) are latched in the INPREG output ; register. ; ;INPUTS ;============================================= ; controls FASTCLOCK CLOCK PIN 33 ; SS MAP output enable. When is 1, SSMAP output ; is disabled and therefore IR_D bus is enabled for ; output. It is used as FOEPIN, since it is high active FOEPIN SSOE_ PIN 6 NODE vdatoe INPUTPIN MAXROADR PIN 13 INPUTPIN MAXROADW PIN 15 ; Input REgister Clock Enable, this low active signal ; from the INPUT XEPLD clocks the SS MAP data into the ; input pin registers CEPIN /IRECE_ PIN 159 ; high active singal from VME, asserted while VME wants to ; read the SS MAP, it enable outputs to the VME data bus INPUTPIN SSRVME PIN 11 ; reset at INIT or power on INPUTPIN RESET PIN 79 ; flags test mode, is =1 while in test mode INPUTPIN TMODE PIN 78 ; from microsequencer, End Event RESET INPUTPIN EERESET PIN 76 ; Input Register Enable, has the same timing and meaning ; as IRECE_, but opposite polarity and is received on a normal ; input pin for internal use INPUTPIN (RCLK=CLOCK) IRE PIN 122 ; End Event bit from the INPUT XEPLD, with the same timing ; as data (IR_D) flags that an End Event word has been found ; in input, therefore it comes without IRE_ INPUTPIN (RCLK=CLOCK) EE_D PIN 117 NODE EE_Di ; VME address bit that overrides EEIN output while in ; test mode (at the next clock positive edge!) (=USQA11) INPUTPIN EEINVME PIN 55 ; VME address bit that overrides NEWHIT output while in ; test mode (at the next clock positive edge!) (=USQA12) INPUTPIN NEWHVME PIN 56 ; spare VME address bits that override SPR_USQAnn while in ; test mode (at the next clock positive edge!) INPUTPIN VME_USQA13 PIN 57 INPUTPIN VME_USQA14 PIN 58 INPUTPIN VME_USQA15 PIN 59 INPUTPIN VME_USQA16 PIN 60 ; spare inputs flags for microsequencer RAM INPUTPIN SPR_USQA13 PIN 62 INPUTPIN SPR_USQA14 PIN 64 INPUTPIN SPR_USQA15 PIN 66 INPUTPIN SPR_USQA16 PIN 68 ; data to/from SS_MAP IOPIN (PINFBK RCLK=CLOCK CE=IRECE_ FOE=SSOE_) IR_D0 PIN 113 IOPIN (PINFBK RCLK=CLOCK CE=IRECE_ FOE=SSOE_) IR_D1 PIN 114 IOPIN (PINFBK RCLK=CLOCK CE=IRECE_ FOE=SSOE_) IR_D2 PIN 115 IOPIN (PINFBK RCLK=CLOCK CE=IRECE_ FOE=SSOE_) IR_D3 PIN 116 IOPIN (PINFBK RCLK=CLOCK CE=IRECE_ FOE=SSOE_) IR_D4 PIN 108 IOPIN (PINFBK RCLK=CLOCK CE=IRECE_ FOE=SSOE_) IR_D5 PIN 109 IOPIN (PINFBK RCLK=CLOCK CE=IRECE_ FOE=SSOE_) IR_D6 PIN 111 IOPIN (PINFBK RCLK=CLOCK CE=IRECE_ FOE=SSOE_) IR_D7 PIN 112 IOPIN (PINFBK RCLK=CLOCK CE=IRECE_ FOE=SSOE_) IR_D8 PIN 104 IOPIN (PINFBK RCLK=CLOCK CE=IRECE_ FOE=SSOE_) IR_D9 PIN 105 IOPIN (PINFBK RCLK=CLOCK CE=IRECE_ FOE=SSOE_) IR_D10 PIN 106 IOPIN (PINFBK RCLK=CLOCK CE=IRECE_ FOE=SSOE_) IR_D11 PIN 107 IOPIN (PINFBK RCLK=CLOCK CE=IRECE_ FOE=SSOE_) IR_D12 PIN 101 IOPIN (PINFBK RCLK=CLOCK CE=IRECE_ FOE=SSOE_) IR_D13 PIN 102 IOPIN (PINFBK RCLK=CLOCK CE=IRECE_ FOE=SSOE_) IR_D14 PIN 103 ; data to/from VME to write/read the SSMAP while in test mode IOPIN (PINFBK ) VDATA0 PIN 124 IOPIN (PINFBK ) VDATA1 PIN 126 IOPIN (PINFBK ) VDATA2 PIN 128 IOPIN (PINFBK ) VDATA3 PIN 130 IOPIN (PINFBK ) VDATA4 PIN 132 IOPIN (PINFBK ) VDATA5 PIN 134 IOPIN (PINFBK ) VDATA6 PIN 136 IOPIN (PINFBK ) VDATA7 PIN 138 IOPIN (PINFBK ) VDATA8 PIN 140 IOPIN (PINFBK ) VDATA9 PIN 145 IOPIN (PINFBK ) VDATA10 PIN 147 IOPIN (PINFBK ) VDATA11 PIN 151 IOPIN (PINFBK ) VDATA12 PIN 153 IOPIN (PINFBK ) VDATA13 PIN 155 IOPIN (PINFBK ) VDATA14 PIN 158 ; ; OUTPUTS ;===================================== ; output data to the GLUE OUTPUTPIN IR_Q0 PIN 5 OUTPUTPIN IR_Q1 PIN 7 OUTPUTPIN IR_Q2 PIN 9 OUTPUTPIN IR_Q3 PIN 12 OUTPUTPIN IR_Q4 PIN 14 OUTPUTPIN IR_Q5 PIN 16 OUTPUTPIN IR_Q6 PIN 25 OUTPUTPIN IR_Q7 PIN 27 OUTPUTPIN IR_Q8 PIN 29 OUTPUTPIN IR_Q9 PIN 32 OUTPUTPIN IR_Q10 PIN 34 OUTPUTPIN IR_Q11 PIN 35 OUTPUTPIN IR_Q12 PIN 2 OUTPUTPIN IR_Q13 PIN 3 OUTPUTPIN IR_Q14 PIN 4 ; output flags ; INvalid SS ADDress, to INPUT XEPLD error and ; EE register to signal invalid input data OUTPUTPIN INVADD PIN 119 ; End Event IN flag to microsequencer, with the same ; timing as NEWHIT, the microsequecere will receive ; all the valid NEWHIT one at each clock cycle, and ; then an End Event flag OUTPUTPIN EEIN PIN 44 PARTITION FFB EEIN ; to microsequencer, to warn that a new valid hit ; will be available at next clock rising edge, so ; that the useq will assert INPUT opcode. Must be fast OUTPUTPIN NEWHIT PIN 47 PARTITION FFB NEWHIT ; spare addresses to microsequencer RAM OUTPUTPIN USQA13 PIN 49 PARTITION FFB USQA13 OUTPUTPIN USQA14 PIN 52 PARTITION FFB USQA14 OUTPUTPIN USQA15 PIN 53 PARTITION FFB USQA15 OUTPUTPIN USQA16 PIN 54 PARTITION FFB USQA16 ; diagnostic outputs ; there is a new valid hit on IR_Q, same timing as data OUTPUTPIN IREGDV PIN 71 ; the logic AND of NEW_HIT and !INVADD OUTPUTPIN IR_CE PIN 38 ; ; ***** state machine for layers words NODE LAY_W0 NODE LAY_W1 NODE LAY_W2 NODE LAY_W3 NODE LAY_W4 NODE LAY_W5 OUTPUTPIN SW S1 S2 S3 S4 S5 S6 SEE OUTPUTPIN ENLAY PIN 149 ;====================================== ; ; PLUSASM files imported from ABEL INCLUDE_EQN 'INPRGA.PLD' ; ;======================================== EQUATIONS sw.prld=vcc s1.prld=gnd s2.prld=gnd s3.prld=gnd s4.prld=gnd s5.prld=gnd s6.prld=gnd see.prld=gnd