Module EE_REG
" End Event REGister for AMS INPUT XEPLD
" it provides the word for the OUTPUT XEPLD to be send as EE, all but the
" parity bit that will be computed by the OUTPUT XEPLD
"
" Revision history
"  Mar 1998 : Stefano Belforte - start modifications bookkeeping
"---------------------------------------------------------------------
"

"Global Inputs
	CLOCK     pin ;

"Inputs	
	EE, FREGDV           		pin ; "To knwo when EEword is stored
	GLPAR				pin ; "Computed input parity so far
	FREG0, FREG1, FREG2, FREG3	pin ; "Input bits from input End Event
	FREG4, FREG5, FREG6, FREG7	pin ;
	FREG8,  FREG9	                pin ;
	FREG10, FREG11, FREG12, FREG13  pin ;
	FREG14, FREG15, FREG16, FREG17  pin ;
	FREG18, FREG19, FREG20          pin ;
	HFFF_				pin ; "Hit Fifo Full Flag
	INVADD				pin ; "Invalid Address from INPREG XELD
	TRNCOU				pin ; "Truncated Output from uSEQ
	EERESET                         pin ; "EE register RESET from uSEQ
        RESET                           pin ; "XEPLD reset (INIT or Power on)


"Outputs	

EE0, EE1, EE2, EE3, EE4, EE5, EE6, EE7		pin;
" EE8 is missing here because is the parity to be computed by the output 
EE9, EE10, EE11, EE12, EE13, EE14, EE15, EE16, EE17, EE18, EE19, EE20	pin;

	
"Nodes
EEFIOV	node; "End Event FIfo OVerflow
EEPAER  node; "End Event PArity ERror
EEINVD  node; "End Event INValid Data
EETROU  node; "End Event TRuncated OUtput

EERGAR	node; "End event Error ReGister Asynch Reset

	
"Assignments
" Collect all End Event bits that needs to be changed from
" input stream in one set for common global reset operation
" note that EEFIOV is NOT reset by EERESET since it is a
" persistent error.
	EEREG  = [EEPAER,EEINVD,EETROU];

Equations

" Input parity mismatch (FREG8 XOR GLPAR) must only be flagged when
" End Event word is being stored
	EEPAER := EEPAER # ( (FREG9 # (FREG8 $ GLPAR))  & (EE & FREGDV) );

	EEFIOV := EEFIOV #   !HFFF_ # (FREG11 & (EE & FREGDV) );

	EEINVD := EEINVD #   INVADD # (FREG12 & (EE & FREGDV) );

	EETROU := EETROU #   TRNCOU # (FREG14 & (EE & FREGDV) );

	EEREG.clk = CLOCK;
	EERGAR    = RESET # EERESET;
	EEREG.ar  = EERGAR;

	EEFIOV.clk = CLOCK;
	EEFIOV.ar  = RESET;

" Now define which are the EE output bits, note that the last word
" arrived in input (End Event word from teh Hit input connector) is
" latched in FREG (see FIFO_REG.ABL)

	EE0  = FREG0   ;
	EE1  = FREG1   ;
	EE2  = FREG2   ;
	EE3  = FREG3   ;
	EE4  = FREG4   ;
	EE5  = FREG5   ;
	EE6  = FREG6   ;
	EE7  = FREG7   ;
	EE9  = EEPAER  ;
	EE10 = FREG10  ;
	EE11 = EEFIOV  ;
	EE12 = EEINVD  ;
	EE13 = FREG13  ;
	EE14 = EETROU  ;
	EE15 = FREG15  ;
	EE16 = FREG16  ;
	EE17 = FREG17  ;
	EE18 = FREG18  ;
	EE19 = FREG19  ;
	EE20 = FREG20  ;
End