Module FIFO_REG
"
" Last modify: January 1998 by Stefano Belforte
"
" FIFO REGISTER for the AMS INPUT XEPLD
" This is the register at the ouptut of the INPUT XEPLD, it generates
" the SSMAP address and the needed control signals for the chips that
" take it as input, the INPREG and the input SPY control, data to
" this two chips is sent on separate pins. Pins for the SPY control
" chip are also used to receive the SS address when VME wants to access it.
" define and put equations for FREG and SSADD
"
"Inputs
	FREGE, TMOD, RESET, CLOCK		pin;
	HFQ0, HFQ1, HFQ2, HFQ3, HFQ4, HFQ5	pin;
	HFQ6, HFQ7, HFQ8, HFQ9, HFQ10,HFQ11	pin;
	HFQ12,HFQ13,HFQ14,HFQ15,HFQ16,HFQ17	pin;
	HFQ18,HFQ19,HFQ20,HFQ21,HFQ22           pin;
        HFEF1_,HFEF2_	                        pin;
"NODE

	VMESS					pin;
	EERESET					pin;

"Outputs

	SSADD0, SSADD1, SSADD2, SSADD3, SSADD4, SSADD5	pin;
	SSADD6, SSADD7, SSADD8, SSADD9, SSADD10,SSADD11	pin;
	SSADD12,SSADD13,SSADD14,SSADD15,SSADD16		pin;

	FREG0,  FREG1,  FREG2,  FREG3				pin;
	FREG4,  FREG5,  FREG6,  FREG7,  FREG8,  FREG9,  FREG10	pin;
	FREG11, FREG12, FREG13, FREG14, FREG15, FREG16, FREG17	pin;
	FREG18, FREG19, FREG20					pin;

	EE, EP, LEP, IRE, IRECE_, SPYDV_, FREGDV		pin;
	SS_SEL_							pin;

"InOuts
	INSPD0, INSPD1, INSPD2, INSPD3, INSPD4, INSPD5		pin;
	INSPD6, INSPD7, INSPD8, INSPD9, INSPD10, INSPD11	pin;
	INSPD12, INSPD13, INSPD14, INSPD15, INSPD16		pin;
	INSPD17, INSPD18, INSPD19, INSPD20, INSPD21		pin;
	INSPD22, INSPD23					pin;

"Nodes
	EF						node;
	SS_D0, SS_D1, SS_D2, SS_D3, SS_D4, SS_D5	node;
	SS_D6, SS_D7, SS_D8, SS_D9, SS_D10,SS_D11	node;
	SS_D12,SS_D13,SS_D14,SS_D15,SS_D16		node;
	SSCE						node;

"Macros
	HFEF_ macro {(HFEF1_ & HFEF2_)};

"Assignements
"	FREG     = [FREG20..FREG0];
	HFQ      = [HFEF_,HFQ22..HFQ0];
	SSADD    = [SSADD16..SSADD0];
        SS_D     = [SS_D16..SS_D0];
	FREGHI   = [FREG20..FREG4];
	INSPD    = [INSPD23..INSPD0];
	INSPDLO  = [INSPD16..INSPD0];
	FREGFULL = [EF,EE,EP,FREG20..FREG0];

"============================================================================

Equations

" FIFO REGISTER

" next equation allows resetting also in fast block of 73108, just in case..
" Reset on EERESET to clear EEIN bit.
	FREGFULL    := ( (FREGE & HFQ) # (!FREGE & FREGFULL) ) &
			!(EERESET # RESET);
	FREGFULL.clk = CLOCK;

"---------------------------------------------------------
" Signals to next pipeline stages
" Fifo REGister Data Valid is synchronous with FIFO REGISTER outputs

	FREGDV    := FREGE;
	FREGDV.clk = CLOCK;
	FREGDV.ar  = RESET;

" Last End Packet flags that the PREVIOUS word had EP bit set
" update each time a word is read into fifo register
        LEP       := (LEP & !FREGE) # (HFQ21 & FREGE);
        LEP.pr     = RESET;
        LEP.clk    = CLOCK;

"---------------------------------------------------------
" Output multiplexer for Super Strip ADDresses
" The multiplexer output is latched for maximum speed. Note that
" this will make VME access to the SS MAP more complex because the
" address to the SS MAP will not be transparent anymore
" Do not send End Event word, and only send if is the first after
" End Packet. While in TMOD send if VME is accessing SS MAP.
"
	SSCE     := (!HFQ22 & LEP & FREGE  & !TMOD) # (VMESS & TMOD);
	SSCE.clk  = CLOCK;
	SSCE.ar   = RESET;
	SS_D      = (!TMOD & FREGHI) # (TMOD & INSPDLO);
	SSADD    := (SSADD & !SSCE) # (SS_D & SSCE);
	SSADD.clk = CLOCK;

	IRE      := SSCE;
	IRE.clk   = CLOCK;
	IRE.ar    = RESET;

" clock enable for storing SS MAP RAM data into the INPUT_REGISTER XEPLD
" input pads registers, to be sent togheter with IRE or with VME request for
" RAM read. Since it does not hurt to enable those registers also when the RAM
" is being written use one only control signal (VMESS) for simplicity.

	IRECE_	   := !SSCE;
	IRECE_.clk  = CLOCK;
	IRECE_.pr   = RESET;

" Chip enable to SS MAP RAM's, to be sent togheter with IRE or with
" VME request for RAM read/write. Note that htis signal is exavctely the
" same as IRECE_, but they go to differen pins of the INPUT_REGISTER XEPLD

	SS_SEL_    := !(SSCE # VMESS);
	SS_SEL_.clk = CLOCK;
	SS_SEL_.pr  = RESET;

"
"---------------------------------------------------------
" INput chip to SPy chip Data bus (bi-directional)	

	INSPD    := FREGFULL;
	INSPD.clk = CLOCK;
	INSPD.oe  = !VMESS;

" Data Valid to Spy Buffer: there are data to be spied on the INSPD bus
	SPYDV_     := !FREGDV;
	SPYDV_.clk  = CLOCK;
	SPYDV_.pr   = RESET;

End