TITLE INPUT CHIP INPUT XEPLD ; INPUT XEPLD chip for the AMS board. Xilinx 73144-7PQ16 ; ; LAST MODIFICATION: January 1998 by Stefano Belforte ; ; This chip handles the input hit flow. It reads data from the HIT FIFO ; and passes them to the SS RAM and to the HIT SPY. ; Hit data flow from FIFO to the internal fifo register (FREG), is handled by ; the FIFO_CTR state machine, via the HFREN_ enable to the FIFO and the ; FREGE clock enable to the fifo register. Then data flow is completely ; data driven, the FREGE enable pushes the data in the following SSADD register ; via the SSCE clock enable. The SSADD register is the output register of this ; chip and provides the adddress to the SS RAM. Between the FREG ; and the SSADD registers, is a multilexer that allows data to the ; SS RAM to be sent from VME via the SPY data bus. ; At the same time as data are stored in the FREG, the input parity is ; also computed. This takes two clock cycles: during the first clock cycle ; the bitwise XOR of the input is performed in parallel on 6 groups of 4 ; bits and the result is stored at the clock rising edge in the registers ; PARITY0-PARITY5. During the next clock cycle the 6 are combined in a ; global GLPAR singal which is XOR'ed with its previous value to give the ; new current parity. On End Event, GLPAR is instead FASTCLOCK CLOCK PIN 33 ;INPUTS ;============================================================== ;general controls INPUTPIN RESET, TMOD PIN 15 104 ;from fifo INPUTPIN (FI) HFEF1_ PIN 11 INPUTPIN (FI) HFEF2_ PIN 17 INPUTPIN HFFF_, HFPAF_ PIN 18 19 INPUTPIN HFQ0, HFQ1, HFQ2, HFQ3, HFQ4, HFQ5 PIN 73 72 71 69 67 66 INPUTPIN HFQ6, HFQ7, HFQ8, HFQ9, HFQ10,HFQ11 PIN 64 63 62 57 55 43 INPUTPIN HFQ12,HFQ13,HFQ14,HFQ15,HFQ16,HFQ17 PIN 38 37 36 32 30 28 INPUTPIN HFQ18,HFQ19,HFQ20,HFQ21 PIN 26 24 23 22 INPUTPIN (FI) HFQ22 PIN 13 ; error flags in INPUTPIN INVADD PIN 103 INPUTPIN TRNCOU PIN 105 ;controls from VME INPUTPIN VMESS PIN 16 INPUTPIN HREVME PIN 29 INPUTPIN WERRREG PIN 4 INPUTPIN WEREREG PIN 136 INPUTPIN RERRREG PIN 133 INPUTPIN REREREG PIN 145 INPUTPIN RFSMREG PIN 142 INPUTPIN RFIFREG PIN 138 ;control from microsequencer INPUTPIN HPOP PIN 139 INPUTPIN EERESET PIN 140 ;I/O ;============================================================== ; data bus to/from spy buffer IOPIN (PINFBK) INSPD0 , INSPD1 , INSPD2 PIN 74 75 76 IOPIN (PINFBK) INSPD3 , INSPD4 PIN 77 78 IOPIN (PINFBK) INSPD5 , INSPD6 , INSPD7 PIN 79 82 83 IOPIN (PINFBK) INSPD8 , INSPD9 PIN 84 85 IOPIN (PINFBK) INSPD10, INSPD11, INSPD12 PIN 86 87 88 IOPIN (PINFBK) INSPD13, INSPD14 PIN 89 90 IOPIN (PINFBK) INSPD15, INSPD16 PIN 91 92 OUTPUTPIN INSPD17, INSPD18, INSPD19 PIN 93 95 96 OUTPUTPIN INSPD20 PIN 97 OUTPUTPIN INSPD21, INSPD22 PIN 98 101 OUTPUTPIN INSPD23 PIN 102 ;VME data bus IOPIN (PINFBK) VDATA0, VDATA1, VDATA2, VDATA3 PIN 151 153 155 158 ;OUTPUTS ;============================================================= ;SSMAP address OUTPUTPIN SSADD0, SSADD1, SSADD2 PIN 60 59 58 OUTPUTPIN SSADD3, SSADD4, SSADD5 PIN 56 53 52 OUTPUTPIN SSADD6, SSADD7, SSADD8 PIN 49 47 156 OUTPUTPIN SSADD9, SSADD10,SSADD11 PIN 154 152 150 OUTPUTPIN SSADD12,SSADD13,SSADD14 PIN 149 148 146 OUTPUTPIN SSADD15,SSADD16 PIN 144 143 OUTPUTPIN SS_SEL_ PIN 54 ;FIFO read enable. Use fast block, give FIFO plenty of time. OUTPUTPIN HFREN_ PIN 5 PARTITION FFB HFREN_ ; flags to microsequencer (actually via INPREG XEPLD). ; Use fast block, just in case has to go to RAM OUTPUTPIN EE PIN 3 PARTITION FFB EE ;End Event word to Output XEPLD OUTPUTPIN EE0, EE1 PIN 135 134 OUTPUTPIN EE2 PIN 132 OUTPUTPIN EE3 PIN 131 OUTPUTPIN EE4 PIN 128 OUTPUTPIN EE5 PIN 126 OUTPUTPIN EE6 PIN 125 OUTPUTPIN EE7 PIN 124 ; EE8 is missing here because is the parity to be computed by the output OUTPUTPIN EE9, EE10, EE11, EE12 PIN 123 122 119 117 OUTPUTPIN EE13, EE14, EE15, EE16 PIN 116 115 114 113 OUTPUTPIN EE17, EE18, EE19, EE20 PIN 112 108 107 106 ;controls to INPREG XEPLD and to Spy Buffer OUTPUTPIN IRE PIN 44 OUTPUTPIN IRECE_ PIN 39 OUTPUTPIN SPYDV_ PIN 42 ;to P3 connector OUTPUTPIN ERRORLINE_ PIN 65 ;to LED's OUTPUTPIN ERRLIGHT PIN 50 ;Diagnostic outputs OUTPUTPIN LEP, FREGE PIN 14 45 OUTPUTPIN FREGDV PIN 6 ;INTERNAL NODES ;============================================================ NODE FREG4 FREG5 FREG6 FREG7 FREG8 FREG9 FREG10 NODE FREG11 FREG12 FREG13 FREG14 FREG15 FREG16 FREG17 NODE FREG18 FREG19 FREG20 EP NODE PARITY0 PARITY1 PARITY2 PARITY3 PARITY4 PARITY5 PARTITION FFB SSADD0, SSADD1, SSADD2, SSADD3, SSADD4, SSADD5 PARTITION FFB SSADD6, SSADD7, SSADD8, SSADD9, SSADD10,SSADD11 PARTITION FFB SSADD12,SSADD13,SSADD14,SSADD15,SSADD16 PARTITION FFB IRE, IRECE_, SS_SEL_ PARTITION FB LEP ;---------------------------------------------------------------------------- ;============================================================================ ; ; PLUSASM FILES IMPORTED FROM ABEL ; INCLUDE_EQN 'FIFO_CTR.PLD' INCLUDE_EQN 'FIFO_REG.PLD' INCLUDE_EQN 'EE_REG.PLD' INCLUDE_EQN 'VME_REG.PLD' ;============================================================================ ; ; PLUSASM FILES IMPORTED AS SUCH ; INCLUDE_EQN 'PARITY.PLD' ; ;========================================================================== ; EQUATIONS ERRGTO.PRLD = GND ERRGID.PRLD = GND ERRGPE.PRLD = GND ERRGFO.PRLD = GND ENRGTO.PRLD = GND ENRGID.PRLD = GND ENRGPE.PRLD = GND ENRGFO.PRLD = GND