Module VME_REG
"
"VME_REGister for the AMS INPUT chip
"
" Revision history
"  Jan 1998 : Stefano Belforte - start modifications bookkeeping
"  4 Mar 98 : S. Belforte  - make ERRORLINE low active since new ABTE16245
"                            open collector driver is not inverting
"  1 May 98 : S. Belforte  - clear error register also with RESET
"---------------------------------------------------------------------
"
"
"Global Inputs
	CLOCK     pin ;
"Inputs	
	EE, FREGDV           	pin ; "To know when End Event is stored
        RESET                   pin ; "XEPLD reset (INIT)

	GLPAR, FREG8		pin ; "Computed and input parity
	INVADD		        pin ; "Invalid Address from INPREG XELD
	TRNCOU			pin ; "Truncated Output from uSEQ

	WERRREG			pin ; " Write ERRor REGister
	WEREREG			pin ; " Write ERror Enable REGister
	RERRREG			pin ; " Read ERRor REGister
	REREREG			pin ; " Read ERror Enable REGister
	RFSMREG			pin ; " Read Fifo State Machine REGister
	RFIFREG			pin ; " Read FIFo status REGister
	FSMB0, FSMB1		pin ; " Fifo State Machine Status bits
	HFEF1_, HFEF2_, HFPAF_, HFFF_    pin ; " Hit Fifo EF, PAF, FF
				      " Empty Flag, PArtial Full, Full FLag
"Outputs
	ERRORLINE_		pin; "To Freeze controller through P3
	ERRLIGHT		pin ; " To ERROR LED, active if any error is on
"InOut
	VDATA0, VDATA1, VDATA2, VDATA3	pin; "Internal VME data bus

"Nodes
" abbreviations: FO = Fifo Overflow
"                PE = Parity Error
"                ID = Invalid Data
"                TO = Truncated Output
	ERRGFO, ERRGPE, ERRGID, ERRGTO node; "ERror ReGister FO PE ID TO
	ENRGFO, ENRGPE, ENRGID, ENRGTO node; "Error Enable ReGister FO PE ID TO
        ERRESET                  node ;      "Error register reset
	VMEREAD			 node ;

"Macros
	HFEF_ macro {(HFEF1_ & HFEF2_)};
"Assignements
" make short busses 4 bits as well for final OR, so pad with zeroes
" REMEMBER: bit ordering must be the same: MSB to LSB
	VMEDATA = [VDATA3..VDATA0]		;"VME DATA bus
	ERRENA  = [ENRGTO,ENRGID,ENRGPE,ENRGFO]	;"ERRor ENAble register
	ERROR   = [ERRGTO,ERRGID,ERRGPE,ERRGFO]	;"ERROR register
	FSMS    = [0,0,FSMB1,FSMB0]		;"Fifo State Machine register
	FIFO    = [0,HFFF_,HFPAF_,HFEF_]	;"FIFO status register

"===========================================================================
Equations	

" Error Register: Store errors as 1s soon as they appear, reset on VME write

	ERRGFO    := ERRGFO # !HFFF_;
"Parity error is only valid after storing an End Event word in Fifo Register
	ERRGPE    := ERRGPE # ((FREGDV & EE ) & (FREG8 $ GLPAR));
	ERRGID    := ERRGID # INVADD;
	ERRGTO    := ERRGTO # TRNCOU;

	ERRESET  = WERRREG # RESET;
	ERROR.clk = CLOCK;
	ERROR.ar = ERRESET;

"Error Enable Register: VME Write (WEREREG) is a clock enable, keep current
" value until VME loads new one from VMEDATA bus. No reset.

	ERRENA := (ERRENA & !WEREREG) # (VMEDATA & WEREREG) ;
	ERRENA.clk = CLOCK;

"Error line for the P3 backplane, global OR of the AND of each
" error bit with its enable

	ERRORLINE_ = !( (ERROR & ERRENA) > 0 );

"Error flag for the front panel LED, light if any error bit is on

	ERRLIGHT = ERROR > 0;
" VME reads, just a multiplexer and a tri-state buffer

	VMEREAD = RERRREG # REREREG # RFSMREG # RFIFREG	; "3-state enable

	VMEDATA = (ERROR & RERRREG) # (ERRENA & REREREG)	
                # (FSMS  & RFSMREG) # (FIFO   & RFIFREG); "4-way mux
	VMEDATA.oe = VMEREAD				; "3-state buffer

End