25/02/98

I copied at the end all what I found still to be done.



11 06 1997 revision 28 janvier 1998
*****VME_CTR
FREEZE  not yet
- add the possibility to send it by VME. 
	needed :        -1 OUTPUTPIN for ORFREEZE
			-1 write function decod.
££ ??

//RESET  OK       
//- different VMEreset :  ## for all but FIFO and POINTERS (ivadat0=1)
//							ARESET PIN27
//			## 1 for FIFO (ivdata0=0)       FRESET PIN25

$$(7/97)new RESET 07/98
$$reset for FIFO and all (ivdata0=1), reset all BUT FIFO (ivdata0=0)
$$ARESET PIN25  (OK in vme.pld)
	
$$(7/97)INIT  OK 
$$- change the input to LEVEL: as long as INIT , RESET all (still synchronized)

$$(7/97)IVADD16 moved from PIN139 to PIN36

$$AM  not yet     
$$- retirer le bit AM2

$$*****INPUT      
$$(6/97)EF_     
$$- OR of the 2 Fifos
	needed: 1 wire between FIFO2EF_ and XEPLD PIN17         

££*****INPREG      OK  perhaps change the name of "maxroad" in maxroad and layers"   
$$(7/97)LAYER WORD 
$$- send at the end of an event words with only the layer, choosen by VME
$$     needed:    -2 INPUTPINs for maxroadr and maxroadw (PIN13 and PIN15)
$$		-function maxroad used
$$ pin ssrvme is pin 11 in inpreg.pld
	
$$//*****OSPY and HSPY    
$$//- inside has been changed in order that the pointers only resetted at the 
$$//same time as FIFO and not always with RESET.
$$ we have to choose if the pointers have to be reset only by write; in Pisa
$$   I thought you wanted to reset it with areset, we can change easily;
$$  we just have to decide. 



	MODIF AMS
12/12/97 revision january 1998

$$#-Electrostatic discharge 2*1Mohm  in serial to gnd	
££#-stiffener				

$$-connectors vme 5 rows-- geographical addresses from P1
££-fuse picofuse
££-transorber
$$-buffers for addresses and datas: ABTE or ABT(open collector)
$$-datas vme proms 24-31
$$-pull up resistors for DV_down
$$-address17/I near glue to be tied to gnd (R31=gndl)
$$-freeze= A3, init=A1, error=A2 , from p3 to p2 
$$-add clock to A2 on P3
$$-new P3 pin assigment
$$-SOIC sockets everywhere
££ some capas still dip to be found in the schematic
$$(7/97)put the last modifications for Z-layers
££- add switch to disable HOLD function on output

££-shorter PCB trace between roboclocks		*
££-quartz socket for small and big ones
££-length for microseq clock same as the others	*
££-VCC island for P1 VCC
££-chamfer
$$- remove patch vias on HOLD for input and output (J6 and J5)

FRONT PANEL
££-new led placement and color
$$-modify the logic as found.
££- test of the modified logic.
££-new connectors, drivers receivers
$$- remove pull_up/pull_down resistors on
    output hold (LVDS does not need them)
££-hole for numeric display
££-front panel without gnd connection

$$-spurious INIT at power on
$$ add mreset push button
$$ change polarity of gead in vme xepld

$$-fuse picofuse // Thomas will take one in Fermilab to have the good footprint
$$-transorber    // Thomas will take one in Fermilab to have the good footprint
$$ change P3 5rows
$$ KEL partialy changed

STILL TO BE DONE 25 2 98

A) TO BE DONE BY ME


££ add test points


I'm waiting for a decision.

££-new led placement and color
££ write of maxroad with Tmod only ??
££ which stiffener ?

B) CHECK ?

££- add switch to disable HOLD function on output. WE do nothing, is it ?
££FREEZE  not yet
- add the possibility to send it by VME. 
	needed :        -1 OUTPUTPIN for ORFREEZE
			-1 write function decod.

C) TO BE GIVEN TO FRANK 
££ pins holes for fuse
££ drawing of ESD has to be given to Frank.   
££-stiffener	
££-shorter PCB trace between roboclocks		*
££-quartz socket for small and big ones
££-length for microseq clock same as the others	*
££-VCC island for P1 VCC
££-chamfer
££-hole for numeric display
££-front panel without gnd connection

 DOCUMENTATION
----------------
 update AMS specifications.
 update block diagram for INPUT chip (Stefano)
 update block diagrams for HSPY_CT, OSPY_CT (Annnie)
                        

legend:
// june 1997, but changed after
* test on prototype first
# ask to bob de maat
££ to be done
$$ done in new schematic