module ospy_co
title   ' counter for ospycounter 8/10/ 96 modif 13/1/98 for reset                      '

                  ospy_co    device   ;
"INPUT for counter
        clock           pin ;
	init		pin;
	freeze		pin;	"freeze allow to read spy during input	                              	    
	vmeopoiw	pin;	"controlto read ospy pointer	

"node inermediaire
	clrcount	node;
	                    			    
"OUTPUTS of counter
        q16,q15,q14,q13,q12,q11,q10,q9		pin istype 'reg,xor';
	q8,q7,q6,q5,q4,q3,q2,q1,q0		pin istype 'reg,xor';
	carry					pin istype 'reg';
	
"INPUT  enable for clock with the same timing that data from out
	outdv_					pin;

"OUTPUT enable for clock to write in ospy with the same timing that datas
	ospyenwe_ 				pin;	
	

"NODE
	carrylo,ispyen			pin;
	ispyqwen,iispyqwen		pin istype 'reg';
        H,L,X,Z,C,P   = 1,0,.X.,.Z.,.C.,.P.;

        q	=[q16..q0] ;
        qlo	=[q13..q0] ;		"lower bits can be calculate in 1 stage
        qhi	=[q16,q15,q14];
                                                             
xor_factors " to force using of xor for counting
	q:=q;        
equations

"ADDRESS CONTROL

	ispyen=!outdv_ & !freeze;
	
	ispyqwen   := ispyen;
	ispyqwen.clk= clock;
	ispyqwen.ar = init;
	
	iispyqwen   := ispyqwen;
	iispyqwen.clk= clock;
	iispyqwen.ar = init;

	ospyenwe_    = !iispyqwen;

" COUNTER 
	carry	:= (q==^h1FFFF);		"memory of maxaddress
	carry.clk= clock;
	carry.ar = clrcount;	

        qlo	:=( (qlo+1) & ispyqwen ) # ( qlo & !ispyqwen ); 
	qhi	:=( (qhi+1) & ispyqwen & carrylo ) 
		# ( qhi     & !(ispyqwen & carrylo) );
	
	carrylo  = (qlo==^h3FFF);                                                  
	q.clk	 = clock;
	clrcount = vmeopoiw;    
	q.ar	 = clrcount;

end