From Annie.Leger@physics.unige.ch Tue Feb 2 02:40:16 1999 Date: Wed, 14 Jan 1998 16:03:53 +0100 From: Léger Annie To: "STEFANO BELFORTE - TEL +39-50-880.305 - INFN PISA" Subject: [Fwd: Minutes] Resent-Date: Wed, 14 Jan 1998 16:03:55 +0100 (MET) Resent-From: belfo@pi.infn.it Resent-To: belfo@galileo.pi.infn.it [ Part 2: "Included Message" ] Date: Wed, 14 Jan 1998 08:16:21 -0600 From: Bob DeMaat To: Annie.Leger@physics.unige.ch Cc: demaat@FNAL.GOV Subject: Re: Minutes Hello Annie, Apparently I didn't update all the files that hold the pointers. I apologize for this. Here are the notes from the meeting. Please send me any necessary corrections. Thank you, Bob Wednesday, October 22, notes Present: Xin Wu, Annie Leger, Aesook Byon-Wagner, Bob Downing, Bob DeMaat, Jim Patrick Xin Wu and Annie Leger met with the PCBCP to review the AMS (Associative Memory Sequencer) module. The panel was provided with the following materials: Prototype of the AMS module Schematic diagrams for the printed circuit board High-level view of the date flow and control Plots of the printed circuit board layers Schematic diagrams of programmable logic circuitry Connectors: The prototype has two 50-pin 100-mil connectors on the front panel. Both connectors are completely filled with differential signals. In consultation with the University of Chicago, a 52-pin 50-mil connector has been selected to be used instead. The additional pins will be used for a ground path. The J3 connector on the prototype is the traditional 96-pin VMEbus-style connector. The production version of the AMS will use the 160-pin version. The AMS will need the new version of the front panel. Information is needed by Xin Wu and Annie. A fuse and a transorb will be added. Information is required. ESD strips and resistors need to be added. Information is required. A VIPA crate is needed. Arrangements will be made to send one. A stiffener like that being developed be Terri Shaw's group will be used. Drawings or a sample need to be provided. The prototype board is bowed by the front panel which is not mounted properly. This is probably due to the holes not being in the required locations. The upper and lower corners of the printed circuit board, nearest the backplane need to be chamfered at a 45-degree angle. This will reduce friction as the board is being inserted into the card guide and will reduce the risk of a corner of the board catching on the ESD contact in the card guide and damaging it. The Xilinx chips that are currently being used are known to be going obsolete in two years. Either the design should be changed to be able to utilize a newer chip or we must ensure that enough spares are purchased to cover the likely needs of the experiment over the AMS' useful life. The VMEbus interface is A32/D32. The AMS responds to address modifiers 09 and 0B. Supervisor mode will be added. Module ID of the production version will be implemented in accordance with CDF2388. On the prototype, the module ID information appears on data bits 7-0. However, on the production version the information will need to appear on data bits 31-24. Maintenance: The AMS will be maintained in the same fashion as most of the SVT. Spares of the AMS will be kept at Fermilab. There will be an SVT test stand here at Fermilab and another at Geneva. Broken AMS boards will be sent to Europe for repair. In operation, the microsequencer code will be downloaded to the AMS via the VMEbus. The SVT group will develop diagnostic software. The AMS uses 4 amps of +5 volt power. The on-board clock runs at 36 MHz on the prototype. This may change over time. A Xilinx chip drives the bus directly on the prototype. ABTE chips will be added to the design for buffering the bus signals. The VITA documentation discusses this approach. Jim Patrick points out that some modules have already been designed that output garbage on "unused" bits so he must assume this while developing software. However, zeroes would be better and the prefered choice for unused bits. A total of 12 AMS modules will be used in the system. The AMS will generate a bus error if a master attempts to access a bad address in the AMS' address space. Keying information will need to be provided to Annie and Xin Wu. ================================================================= If you find inaccuracies (or omissions) you would like to have corrected, please send comments to Bob DeMaat. demaat@fnal.gov fnald::demaat