TITLE  uSEQUENCER OUTPUT REGISTER

CHIP  usq_oreg  XEPLD
;
; This chip contains 8 bits of the AMS microsequencer output register
; It also provides the buffer and multiplexer needed to read/write the
; useq RAM from VME, while keeping all connections to the RAM chips a
; one_pin-to-one_pin wire.
; The status register is zeroed when RESET is asserted, and is also
; kept zeroed as long as TMODE is asserted.
; Up to 10 bits are possible in order to fit a 7336 chip.
; 
;INPUTS
;=============================================
; controls

FASTCLOCK CLOCK						PIN  5

; reset at INIT or power on
INPUTPIN RESET						PIN  3
; flags test mode, is =1 while in test mode
INPUTPIN TMODE						PIN  4

; micro (U) SeQuencer RAM Output Enable from VME
; This signal is a low active enable for the RAM chips,
; but to the USQ_SREG XEPLD it looks like an
; high active signal that enable output toward
; the useq RAM data bus, when VME wants to write it.
FOEPIN	USQOE_						PIN 39

; micro (U) SeQuencer Read from VME
; high active signal that enable output toward
; the VME data bus, when VME wants to read the useq RAM.
FOEPIN	USQRVME						PIN 40

;data to/from microsequencer RAM		
IOPIN (PINFBK FOE=USQOE_) D0 D1 D2 D3			PIN 29 30 33 34
IOPIN (PINFBK FOE=USQOE_) D4 D5 D6 D7			PIN 35 36 37 38

; data to/from internal VME data bus
IOPIN (PINFBK FOE=USQRVME) VD0 VD1 VD2 VD3		PIN  8  9 11 12
IOPIN (PINFBK FOE=USQRVME) VD4 VD5 VD6 VD7		PIN 13 14 15 16

;
; OUTPUTS
;=====================================

OUTPUTPIN Q0 Q1 Q2 Q3					PIN 24 25 26 27
OUTPUTPIN Q4 Q5 Q6 Q7					PIN 22 20 19 18

;==========================================
; PLUSASM files imported from ABEL
;

INCLUDE_EQN 'usq_orga.pld'
;
;======================================
;
EQUATIONS