Module USQ_ORGA

title 'microSEQUENCER OUTPUT REGISTER ABEL EQUATIONS'

" ABEL file for USQ_OREG chip for AMS
" S.Belforte - Jan 1997

USQ_REG device;

"Inputs
	CLOCK, RESET, TMODE			pin;
	D0, D1, D2, D3, D4, D5, D6, D7		pin;
	
"Outputs
	VD0, VD1, VD2, VD3, VD4, VD5, VD6, VD7	pin;
	Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7		pin;

"Nodes
	REG_RESET			node;

"Assignements

	D    = [D7..D0] ;
	Q    = [Q7..Q0] ;
	VMEDAT = [VD7..VD0] ;

Equations

" register asyncronous reset
	REG_RESET = RESET # TMODE;

" register content will be simly the D input, both
" in normal operation and in TMODE

	Q    := D ;
	Q.clk = CLOCK ;
	Q.ar  = REG_RESET;

"
" output toward the RAM data bus will be the VME data, proper enable
" is declared in the top level PLD file via FOE= statement. This is the
" only way to have output enable in a 7336.

	D     =  VMEDAT ;

"
" to the VME data bus will send the D input when the useq RAM is being read
" tri-state is controlled from top level PLD as above
	VMEDAT    = D ;

End