TITLE  uSEQUENCER STATUS REGISTER

CHIP  usq_sreg  XEPLD
;
; This chip contains 4 bits of the AMS microsequecner status register
; It also provides the buffer and multiplexer needed to read/write the
; useq RAM from VME, while keeping all connections to the RAM chips a
; one_pin-to-one_pin wire.
; The status register is zeroed when RESET is asserted, and is also
; kept zeroed as long as TMODE is asserted.
; Only seven bits at maximum are possible in order to fit a 7336 chip.
; Since we need 8, will use two chips with 4 bits each.
; 
;INPUTS
;=============================================
; controls

FASTCLOCK CLOCK						PIN  5

; output enable for the VME data bus, it has to be
; connected to the VD_OE_OUT pin, which has the internally
; geneated enable, properly obtained combining USQRVME,
; RUSQREG and TMODE. This unpleasant trick is needed to
; avoid an interconnect error in XACT.
FOEPIN VD_OE_IN						PIN 40

; reset at INIT or power on
INPUTPIN RESET						PIN  3

; flags test mode, is =1 while in test mode
INPUTPIN TMODE						PIN  4

; micro (U) SeQuencer RAM Output Enable from VME
; This signal is a low active enable for the RAM chips,
; but to the USQ_SREG XEPLD it looks like an
; high active signal that enable output toward
; the useq RAM data bus, when VME wants to write it.
; It also enables the internal VME address bus to be
; sent in output in place of the microsequencer status
; register in order to be used as RAM address
FOEPIN USQOE_						PIN 39

; the following pin must be externally tied to USQOE_, it is a
; normal input for internal logic (can't use FOEPIN in logic)
INPUTPIN USQOE_IN					PIN 42

; micro (U) SeQuencer Read from VME
; high active signal that enable output toward
; the VME data bus, when VME wants to read the useq RAM.
; It also enables the internal VME address bus to be
; sent in output in place of the microsequencer status
; register in order to be used as RAM address
INPUTPIN USQRVME					PIN  2

; Read micro (U) SeQuencer status REGister
; high active signal from VME to enable placing the
; status register content on the internal VME data bus
INPUTPIN RUSQREG					PIN 44

;address from internal VME address bus
INPUTPIN VA0 VA1 VA2 VA3				PIN 35 36 37 38

;data to/from microsequencer RAM
IOPIN (PINFBK FOE=USQOE_) D0 D1 D2 D3			PIN 27 26 25 24

; data to/from internal VME data bus
IOPIN (PINFBK FOE=VD_OE_IN) VD0 VD1 VD2 VD3		PIN 14 13 12 11

;
; OUTPUTS
;=====================================

; Current status bits, to be sent to useq RAM address
OUTPUTPIN Q0 Q1 Q2 Q3					PIN 29 30 33 34

; output enable for VD0-VD3
OUTPUTPIN VD_OE_OUT					PIN 43


;==========================================
; PLUSASM files imported from ABEL
;

INCLUDE_EQN 'usq_srga.pld'
;
;======================================
;
EQUATIONS