Module v_co_dec Title ' counter for address block transfert and address decod' "2 /10 1996 " " 13-Jan-1997: S.Belforte use CLOCK in place of !CLOCK2 for INIT1 " to improve timing " " MAY 1997 change of INIT " JUNE 1997 split of RESET in : ARESET, and FRESET; "JULY 97 Freset is not used, not necessary "IVDATA0 -> I/O, writevme_, is directly sent to the direction of "data vme transceivers, IVDATA0 can be used during s4 state. " " RDBRD_ stays now at 0, with ARDSSY, at the end of a write function, " if writevme changes, at the same time as DS, but before DTack " answers.ne marche pas " 16/1/98 essai avec writevme latche au debut du cycle "last modif 24/4/98 v_co_dec device; "INPUT clock pin; freeze pin; " from back panel init pin;" for reset from exterior "INPUT from VME writvme_ pin; wrvmeit_ node istype 'reg'; "INPUT from VME ivdata0 pin;"for tmod reading by vme "and reset choose "ADDRESS MEMORY AND COUNTER "INPUT VME ADDRESS vmeadd23,vmeadd22,vmeadd21,vmeadd20,vmeadd19 pin; vmeadd18,vmeadd17,vmeadd16,vmeadd15,vmeadd14 pin; vmeadd13,vmeadd12,vmeadd11,vmeadd10,vmeadd9 pin; vmeadd8 pin; "this addresses are possibly incremented vmeadd7,vmeadd6,vmeadd5,vmeadd4 pin; vmeadd3,vmeadd2 pin; vmeadd1 pin; "OUTPUT address for AMS " intern address shifted by 2 bits ( or 1 because vmeadd0 doesn't exist) " low address can be internally incremented by a counter " high address is clocked when As and Ds ivadd21,ivadd20,ivadd19,ivadd18,ivadd17 pin istype 'reg'; ivadd16,ivadd15,ivadd14,ivadd13,ivadd12 pin istype 'reg'; ivadd11,ivadd10,ivadd9,ivadd8,ivadd7 pin istype 'reg'; ivadd6 pin istype 'reg'; ivadd5,ivadd4,ivadd3,ivadd2 pin istype 'reg'; ivadd1,ivadd0 pin istype 'reg'; "NODE for the increment q5,q4,q3,q2,q1,q0 pin istype 'xor'; "NODES for memory of decodage during block transfert decoblo2,decoblo4,decoblo5 pin istype 'reg'; decoblo6,decoblo7,decoblo8 pin istype 'reg'; "******FSM **** "NODES from FSM to address decod "en for multiplex and outenable....cken 1 clock cycle for clockenabl " cken2 for fiforead which is longer en,cken1,cken2 pin; asadsy,arasaded,euda,as_ pin; ardssy pin; "NODES from FSM to counter load,enincr pin; "****DECOD ADDRESSES FOR BOARD***** "node high bits=0 for registers decod adreg pin;"high bits=0 for registers decod "OUTPUT for board rerrreg,werrreg pin; ";error register (in INPUT) tmodr pin; "outenable for ivdata0 ttmod pin istype 'reg'; tmod pin; tmodl node; init0,init1,init2,init3 pin istype 'reg'; cktmod pin; areset pin istype 'reg';"sync reset vreset pin ; "large signal fifores_ pin istype 'reg';"1 clockcycle rfifreg pin; "read of fifo reg vmeholdr pin; "vme hold read rfsmreg pin; "read fsm input rusqreg pin; "read usq reg pushvme pin istype 'reg'; "vme push out pushvmel node; vmehpoir,vmehpoiw pin; vmeopoir,vmeopoiw pin; rerereg pin; wereregl node; werereg pin istype 'reg'; maxroadr pin; maxroadw pin istype 'reg'; maxrodwl node; vmephir pin; "vme read of sector vmeprom_ pin; "vme read of prom hrevme pin istype 'reg'; "clock for vme fifo vmefifrd pin; "en for vme read of fifo vmehspyr,vmeospyr pin; "en for vme read of spy usqrvme,usqoe_,usqcs_ pin; "read of useq usqwe_ pin istype 'reg';"clock for w ssrvme,ssoe_,vmess pin; "en for vme read of ssram sswe_ pin istype 'reg';"clock for w usqwel, sswel node ; " this pins are for VME data bus transceiver to set the dirction and latch rdbrd_ pin; s11 pin; wrbrd_ pin; "DEFINITIONS H,L,X,Z,C,P = 1,0,.X.,.Z.,.C.,.P.; vmeadd =[vmeadd23..vmeadd1]; vmeaddlo=[vmeadd7..vmeadd2]; vmeaddhi=[vmeadd23..vmeadd8]; ivaddlo =[ivadd5..ivadd0]; ivaddhi =[ivadd21..ivadd6]; q =[q5..q0]; vmeadreg=[vmeadd23..vmeadd6]; decodreg=[vmeadd5..vmeadd2]; decodblo=[vmeadd23..vmeadd19]; decoblo =[decoblo8..decoblo4,decoblo2]; decorclk=[fifores_,pushvme,werereg,maxroadw]; ramclk =[hrevme,usqwe_,sswe_]; equations " COUNTER "increment calculated as soon as possible q=ivaddlo + 1 q0= !ivadd0; q1=ivadd1 $ ivadd0; q2=ivadd2 $ (ivadd1 & ivadd0); q3=ivadd3 $ (ivadd2 & ivadd1 & ivadd0); q4=ivadd4 $ (ivadd3 & ivadd2 & ivadd1 & ivadd0); q5=ivadd5 $ (ivadd4 & ivadd3 & ivadd2 & ivadd1 & ivadd0); " multiplex of increment or vmeadd(load) with chip enable ivaddlo:= (q & enincr ) # (vmeaddlo & load) # (ivaddlo & !enincr & !load); ivaddhi:= (ivaddhi & !load) # (vmeaddhi & load); ivaddlo.clk=clock; ivaddhi.clk=clock; "CONTROL SIGNAL FOR VME " control of datas transceivers: read and write !rdbrd_= (rerrreg #tmodr #rfifreg #vmeholdr #rfsmreg #rusqreg #vmehpoir #vmeopoir #rerereg #maxroadr # vmephir #!vmeprom_ #vmefifrd #vmehspyr #vmeospyr #usqrvme #ssrvme ) ; !wrbrd_ =tmodl #werrreg #vreset #pushvmel #vmehpoiw #vmeopoiw #wereregl #maxrodwl #usqwel #sswel; "CONTROL SIGNALS FOR BOARD "RESET from the back panel P3 init0:=init; init0.clk=clock; init1:=init0; init1.clk=clock; init2:= init1 ; init2.clk=clock; init3:=(init2 ); init3.clk=clock; "REGISTERS "enable signals are not synchronised "cken come from fsm and synchro in a register " signals with l are long signals for transceiver "As all VME signals are undefined after Ds_ is High, some controls for "transceivers can be undefined until Dtack is deasserted. "for register in data transfert we don't have to memory the address adreg =(vmeadreg==0) & euda ; decorclk.clk =clock; cktmod =adreg & !wrvmeit_ & cken1 & (decodreg==2)& !vmeadd1; tmodl =adreg & !wrvmeit_ & en & (decodreg==2)& !vmeadd1; ttmod.clk=cktmod; ttmod.ar=areset; ttmod := H; tmod =ttmod; rerrreg = adreg & wrvmeit_ & en & (decodreg==0)& !vmeadd1; werrreg = adreg & !wrvmeit_ & en & (decodreg==0)& !vmeadd1 ; vreset =(adreg & !wrvmeit_ & en & (decodreg==1)& !vmeadd1); areset :=(adreg & !wrvmeit_ & en & (decodreg==1)& !vmeadd1) # init1 # init2 #init3; fifores_:=!(((adreg &!wrvmeit_& cken1 & (decodreg==1)& !vmeadd1)&!ivdata0) # init2); tmodr = adreg & wrvmeit_ & en & (decodreg==2)& !vmeadd1; rfifreg = adreg & wrvmeit_ & en & (decodreg==3)& !vmeadd1; vmeholdr= adreg & wrvmeit_ & en & (decodreg==4)& !vmeadd1; rfsmreg = adreg & wrvmeit_ & en & (decodreg==5)& !vmeadd1; rusqreg = adreg & wrvmeit_ & en & (decodreg==6)& !vmeadd1; pushvme:= adreg & !wrvmeit_ & cken1 & (decodreg==7)& !vmeadd1 & ttmod; pushvmel= adreg & !wrvmeit_ & en & (decodreg==7)& !vmeadd1 &ttmod; vmehpoir= adreg & wrvmeit_ & en & (decodreg==8)& !vmeadd1; vmehpoiw=(adreg & !wrvmeit_ & en & (decodreg==8)& !vmeadd1); vmeopoir= adreg & wrvmeit_ & en & (decodreg==9)& !vmeadd1; vmeopoiw=(adreg & !wrvmeit_ & en & (decodreg==9)& !vmeadd1); rerereg = adreg & wrvmeit_ & en & (decodreg==10)& !vmeadd1; werereg:= adreg & !wrvmeit_ &cken1 & (decodreg==10)& !vmeadd1 ; wereregl= adreg & !wrvmeit_ & en & (decodreg==10)& !vmeadd1 ; maxroadr= adreg & wrvmeit_ & en & (decodreg==11)& !vmeadd1 ; maxroadw:=adreg & !wrvmeit_ &cken1 & (decodreg==11)& !vmeadd1 & ttmod; maxrodwl =adreg & !wrvmeit_ & en & (decodreg==11)& !vmeadd1 & ttmod; vmephir = adreg & wrvmeit_ & en & (decodreg==12)& !vmeadd1; "for possibility of block transfert, decod has to be memorised decoblo2:= (decodblo==2) ; decoblo4:= (decodblo==4); decoblo5:= (decodblo==5); decoblo6:= (decodblo==6); decoblo7:= (decodblo==7); decoblo8:= (decodblo==8); decoblo.clk=asadsy; decoblo.ar=as_; wrvmeit_:= writvme_; wrvmeit_.clk= asadsy; vmeprom_=!(wrvmeit_ & en & (decoblo2) & !vmeadd18& !vmeadd1) ; hrevme := wrvmeit_ & cken2 & (decoblo4) & ttmod & !vmeadd1 ; vmefifrd = wrvmeit_ & en & (decoblo4) & ttmod & !vmeadd1 ; vmehspyr = wrvmeit_ & en & (decoblo5) &(ttmod#freeze)& !vmeadd1; vmeospyr = wrvmeit_ & en & (decoblo6) &(ttmod#freeze)& !vmeadd1; usqrvme = wrvmeit_ & en & (decoblo7) & ttmod & !vmeadd1 ; usqoe_ =!wrvmeit_ & en & (decoblo7) & ttmod & !vmeadd1 ; usqcs_ = ttmod &!( en & (decoblo7) & !vmeadd1 ); !usqwe_ :=!wrvmeit_ & cken1 & (decoblo7) & ttmod & !vmeadd1 ; usqwel = !wrvmeit_ & en & (decoblo7) & ttmod & !vmeadd1 ; ssrvme = wrvmeit_ & en & (decoblo8) & ttmod & !vmeadd1 ; ssoe_ =!wrvmeit_ & en & (decoblo8) & ttmod & !vmeadd1 ; vmess = en & (decoblo8) & ttmod & !vmeadd1 ; !sswe_ :=!wrvmeit_ & cken1 & (decoblo8) & ttmod& !vmeadd1 ; sswel =!wrvmeit_ & en & (decoblo8) & ttmod& !vmeadd1 ; ramclk.clk=clock; "OUTPUT ON VMEDATA OF TMOD reading ivdata0.oe=tmodr; ivdata0=ttmod; end