Hit Buffer Board #1 - pre-production prototype
pcb version 2.0
assembled in April 1999

ENMAP started with socket, immediately removed. Socket was
awfully bad.

By historical accident this has #1, but is the second board to
be assembled. The first has sockets on all 73144 and was used to
discover the ENMAP problem. This board was made with socket on
ENMAP to allow debugging.

Jun 12 1999: cold solder found on roboclock U64 pins 4/5 1999, fixed by
 pushing.

ENMAP xilinx replaced with final version in July 1999
tested at Fnal in summer 1999 Vertical Slice Test
HRVME xilinx replaced in fall 1999 to fix spurios reset bug
several terminations replaced/removed at the same time
also bypass capacitors for HRVME messed up

very extensively tested in Pisa and Trieste with random test winter 99/00

since February 2000 at Fermilab in B0 SVT crate

Board works but not final.

VMEPLD and HBSPYBUF still not final version
EPROM does not have standard content and would fail standard test

Will need to to come back to Pisa for:
- putting back terminations
- fixing HRVME capacitors
- replacing VMEPLD and HBSPYBUF with final version
- mounting final front panel
- replacing EPROM content with final content
- making sure U64 pins are well soldered

17 Dec 2000: board returns to Pisa. Put new EPROM. OK but last
location is ff instead of 00. Likely bad Eprom, will fix later.
Pass HB quick test.
Send to Eclipse for above update/repair.

10 Feb 2001: board returns from Eclipse to Trieste.
Pass all tests (including 150K iter of random test).
Eprom still fails as before but putting EPROM #18 is OK.

11/12 Feb 2001: passes ~220K iter of random test.
Remove to fix EPROM. Indeed last location of old eprom was wrong
also reading from programmer. Program new eprom chip and replace,
all OK. Run again random test.

12/13/14 Feb 2001: odd problems in output appear. Likely
bad via/solder. Can not fix. See
test logbook http://www.ts.infn.it/~belforte/svt/hb/hb_repair.html.

Board bad.

Will stay in Trieste forever.