Hit Buffer Board #19 - final production board
pcb version 2.1
assembled in Jan 2002 by Verrieri
Xilinxes programmed in May 2001 by Franco
It has the non-IDT tag ram
Tested in Trieste April 2002
Found need to change timing of DNCLK to ENAMP, see logbook.

passed 350K iteration of random test in TS on April 18-19
passed 2010500 (2M) iteration of random test in TS on May 3-5
passed 2.8M random test iteration at 23MHz in TS May 16-21

Board O.K.
Shipped to FNAL on May 23, 2002 (via AMZ).
passed ~4M iteration of random test on B0 test stand at 23MHz

BEWARE: NEEDS NON STANDARD JUMPERS !!!
U66 4F1 = mid (no jumper)
U66 4F0 = low (jumper to GND = upper row)