Hit Buffer to_do. Last update: 23 April 1998 (*X* means Xilinx logic change) 1. Footprint tagram 2. 5-rows P1 and P2 4. Geographical address (a'la AMS): P1, pull-ups, switches, *X* invert in Xilinx ! 5. VME ETL tranceiver 6. ID Prom on data bits 27..31 7. INIT, ERROR, FREEZE on P2 8. INIT and FREEZE low active (add inverter gate) 9. Stiffner 10. Connect EF_ from both fifo's for both Roads and Hits 11. LVDS driver/receivers, no pull-ups, ground return etc. 12. New front panel connectors and placements 13. New LED color/placement 14. *X* Add ETL control lines to VME xilinx 15. Single slot: - crosscheck Samsung footprints - tagrams 16. *X* Error bits persistency (Fifo-Ovf, Lost-Sync) 17. ESD strips 18. Roboclock filter capacitors 19. *X* Check Init protocol 20. Transorber 21. picofuse 22. chamfers 23. *X* Add VME supervisor modes (ignore AM<2>) 24. SOIC wherever sensible 25. quartz socket for small/large (like AMB) 26. Vcc island for P1 Vcc pins. 27. front panel without ground connection 28. update documentation 29. *X* change HOLD_IN_ polarity: LVDS failsage status is HIGH 30. remove test points on unused XIlinx outputs. 31. add ground points all over the board for scope probe ground clip 32. Front panel pin assign. as in XTR to SVT and L2 ... document (and AMS) 33. *X* VME ERROR register cleared by INIT Standing or new problems as of Sep 30 1998 ------------------------------------------ 1. dividere gli OR (U14) per Hit e Roads in 2 chips ? 2. Aggiunger LEDs e mettere i LED multipli come da doc. AMZ. INTERNAL_ERROR ==> modifica a Xilinx ? 3. Leggere stato switches da VME ? ==> modifica a HB_CTNFF ? Aggiunta a VMEPLD ? 4. Lettura Spy Buffers in TMODE ==> add internal freeze to VMEPLD 5. togliere TL7705ACD (reset chip), provare su quello di ora ? 6. verificare che non si posono fare operazioni "distruttive" se non e' in TMODE (PUSHVME ?!) 7. DS_ out in OU4 ==> OUT1 = OUT0=OUT2=OUT3 8. Unificare part HB-AMS-SC-MRG etc.: - HC123 - AS32 - ALS08 - ALS688 al posto di FCT521 ???? DW invece di (Q?)S(?)SOP ?