module HRIVMEL title 'To make the 2 fifos, the AM map, the SS map and RO registers readable from VME' "INPUTS CLK, INIT pin ; HRFQ0, HRFQ1, HRFQ2, HRFQ3 pin ; HRFQ4, HRFQ5, HRFQ6 pin ; HRFQ21, HRFQ22 pin ; HRSPY0 , HRSPY1 , HRSPY2 , HRSPY3 pin ; HRSPY4 , HRSPY5 , HRSPY6 pin ; HRSPY21, HRSPY22 pin ; HEF_0, REF_0, HEF_1, REF_1 pin ; CLRTAG, TRAIL, READY, sm1q0 pin ; FHQ1, HPOK_, FRQ1, RPOK_, IHOLD pin ; HFFULL_, HFHFULL_, RFFULL_, RFHFULL_ pin ; IVADD0, IVADD1, IVADD2 pin ; IVADD14, IVADD17, IVADD18, IVADD19 pin ; "Outputs IVDATA0, IVDATA1, IVDATA2, IVDATA3 pin ; IVDATA4, IVDATA5, IVDATA6 pin ; IVDATA21, IVDATA22, IVDATA31 pin ; "macro HEF_ macro {(HEF_0 & HEF_1)} ; REF_ macro {(REF_0 & REF_1)} ; "Assignments IHRBUS = [ HRFQ22,HRFQ21,HRFQ6..HRFQ0]; HRSPYBUS = [HRSPY22,HRSPY21,HRSPY6..HRSPY0] ; VMEADD = [IVADD2, IVADD1, IVADD0]; VMEREG = [IVDATA22,IVDATA21, IVDATA6..IVDATA0]; HFIFOS = [0, 0, 0, 0, 0, 0, HFFULL_, HFHFULL_, HEF_]; RFIFOS = [0, 0, 0, 0, 0, 0, RFFULL_, RFHFULL_, REF_]; FSMH = [0, 0, 0, 0, 0, 0, 0, FHQ1, HPOK_]; FSMR = [0, 0, 0, 0, 0, 0, 0, FRQ1, RPOK_]; HBSTAT = [0, 0, 0, 0, 0, 0, 0, 0, !IHOLD]; s1_reg = [0, 0, 0, 0, 0, CLRTAG, TRAIL, READY, sm1q0]; Equations " vme registers: VMEREG = (VMEADD == 3) & HFIFOS & !IVADD19 # (VMEADD == 4) & RFIFOS & !IVADD19 # (VMEADD == 5) & HBSTAT & !IVADD19 # (VMEADD == 6) & s1_reg & !IVADD19 # (VMEADD == 0) & FSMH & !IVADD19 # (VMEADD == 1) & FSMR & !IVADD19 # IHRBUS & !IVADD18 & !IVADD17 & IVADD19 # HRSPYBUS & (IVADD18 # IVADD17) & IVADD19; IVDATA31 = HEF_ & !IVADD14 & !IVADD18 & !IVADD17 & IVADD19 # REF_ & IVADD14 & !IVADD18 & !IVADD17 & IVADD19; HRSPYBUS := IHRBUS ; HRSPYBUS.CLK = CLK ; HRSPYBUS.ar = INIT ; End