TITLE NLAST2
AUTHOR  GIANNETTI 
COMPANY INFN
DATE 15-MAY-1995

CHIP   NLAST2   XEPLD;

;           TAGRAM controller
FASTCLOCK  CLK
INPUTPIN RPOKX SM1Q0 READY TRAIL CLRTAG IHOLD  
INPUTPIN (FI) M0 M1 M2 M3 M4 M5 M6 M7
INPUTPIN      SS0 SS1 SS2 
INPUTPIN (FI) HITCN0 HITCN1 HITCN2
OUTPUTPIN   EMPTY
OUTPUTPIN   N2LAST0 N2LAST1 N2LAST2  
OUTPUTPIN   N2LAST3 N2LAST4 N2LAST5 
OUTPUTPIN   N2LAST6 N2LAST7 N2LAST8 N2LAST9 
; TEMP is not necessary in the project; it is there only to provide
; CLK in the simulation file of this chip that has no FF. To be removed
OUTPUTPIN   RLE  TEMP
PARTITION FFB   N2LAST0 N2LAST1 N2LAST2  
PARTITION FFB   N2LAST3 N2LAST4 N2LAST5 
PARTITION FFB   N2LAST6 N2LAST7 N2LAST8 N2LAST9 
PARTITION FFB   RLE EMPTY
INCLUDE_EQN 'NLAST2.PDS'

EQUATIONS
     TEMP:=SS0
     TEMP.CLKF =CLK