Module OUT4
Title 'OUT REG + VME MUX '

"Global Inputs
	CLK		pin ;
"Inputs
	TMOD      	pin ;
	PUSH      	pin ;
	PUSHVME   	pin ;
	EERESET		pin ;
	IVADD19		pin ;	

	ODD0, ODD1, ODD2, ODD3           pin ;

"EPOUT is equivalent to TRAIL (outside the chips the line TRAIL is available)
	OSPY8,   OSPY20,   OSPY21, OSPY22	pin ;
	DATA8,   DATA20,   EPOUT,    EEOUT	pin ;
	IVDATA8, IVDATA20, IVDATA21, IVDATA22	pin ;

"Outputs
	OUT8, OUT20, OUT21, OUT22		pin ;

"Nodes
	ODD4					node ;

"Macro
	OUTPA macro {(ODD0 $ ODD1 $ ODD2 $ ODD3 $ ODD4)}

"Assignments
	DATABUS    = [EEOUT,  EPOUT,  DATA20];
	IVDATABUS  = [IVDATA22..IVDATA20 ];
	OUTBUS     = [OUT22..OUT20];
	OSPYBUS    = [OSPY22..OSPY20];

Equations

" MUX of OUT register  and  VME REG

	OUTBUS := (!TMOD & ((PUSH    & DATABUS  ) # (!PUSH    & OUTBUS))
			# TMOD & ((PUSHVME & IVDATABUS) # (!PUSHVME & OUTBUS))) ;
	OUTBUS.clk = CLK ;

	OSPYBUS = OUTBUS ;

	IVDATABUS = (OUTBUS & !IVADD19) # (OSPYBUS & IVADD19);

	OUT8	:= (!TMOD & ((PUSH    & ((OUTPA & EEOUT) # (DATA8 & !EEOUT))) # (!PUSH & OUT8))
			# TMOD & ((PUSHVME & IVDATA8) #  (!PUSHVME & OUT8))) ;
	OUT8.clk = CLK ;

	OSPY8   =  OUT8 ;
	IVDATA8 = (OUT8 & !IVADD19) # (OSPY8 & IVADD19);

	ODD4.T = !EEOUT & PUSH & ( DATA8 $ DATA20 $ EPOUT ) ;
	ODD4.clk = CLK ;
	ODD4.ar  = EERESET  ;

End