Stefano Belforte's SVT docs

documents for, and wrap up from, the SVT Workshop October 27-28 1998, also summary given at the CDF Collaboratin meeting on Nov 5, 1998

AMS : Associative Memory Sequencer

• AMS PRODUCTION CHIP list of what is needed to send from Pisa to UniGE and what from Geneve to Pisa.
• VME addresses from the Geneve web site.
• VME addresses in more compact Stefano's form.
• list of modifications for next version of AMS (bug fixes, our improvements, CDF pcb review outcome) from Annie.
• An AMS board block diagram showing all the big chips and the main data path, made with the unix free-domain xfig program is availble as gif or encapsulated postscript, or even as the xfig source file
• Clocks, distribution and roboclock settings.
• The AMS internal microsequencer code is stored in RAM. The RAM content is created by a C program. Get here the latest verion of the source code and of the needed header file. Also the state diagram.
• AMS schematics as A3-size gzipped postscript files:
  AMS(top level), Clock_Gen, Convme_5rows, Front_Panel, Glueams_Hard, In_Bus, Input_Control, Micro_Sequencer, Out_Bus, Output, P3, P3conn, Prom_Switch, Vme_Bus, Capa
• Also the scheatics of how the Xilinx elemental bodies have been wrapped into *_xepld bodies with nice shape and big busses:
  hspy_ct_xepld, ospy_ct_xepld, inpreg_xepld, input_xepld, usq_oreg_xepld, usq_sreg_xepld, out_ctr_xepld, vme_ctr_xepld
• Xilinx chips programming. All the details of what is inside the various Xilinx EPLDs.
• AMSglue (aka GLUE3) programming. The internals of the AMSGLUE chip.

AMB: Associative Memory Board

Schematics as gzipped postscript files (A3 format). If you have problems with the postscript file, see the note about my postscript files in the top page.
top level, vme bus, Xilinx EPLD that implemets the VME slave

Summary of talk submitted to the 1998 IEEE Nuclear Science and Medical Imaging conference (or more precisely to the 1998 IEEE Nuclear Science Symposium) in postscript or pdf format. Also the abstract, the LaTex source file and the required latex style. The paper status can be viewed clicking here, paper numer is 1124, but you will need a password (palle1).

HB: Hit Buffer

• list of modifications for production
• VME addresses map
• HB Specification and Design local copy (also as SVT note from the SVT home server).

MRG: Merger

Old from CAEN

• Switch settings
• LVDS<-->TTL adaptor

AM-FPGA project

AMfpga Board

• OGLUE chip: bottom level output glue, ties 64 AMfpga chips from 8 busses and talk to TGLUE on top side.
  • Verilog sources for simulation and Synopsis synthesis: oglue, gl0_2x10, glue2x11, glue2x12, glue2x13, oglue_fsm, oglue_specials_SIMULATION, oglue_specials_SYNOPSIS.

Other stuff